Inverter gating circuit



Aug. 2, 1966 D R, BQYD 3,264,489

INVERTER GATING CIRCUIT Flled OCT.. 215, 1962 2 Sheets-Sheet 1 SQUARE WAVE OSCILLATOR Aug. 2, 1966 D. R. BOYD INVERTER GATING CIRCUIT Filed OCT.. 23, 1962 2 Sheets-Sheet 2 www @1. @swol /241' u/ United States Patent O 3,264,489 INVERTER GATING CIRCUlT Donald R. Boyd, Waukesha, Wis., assignor to Allis- Svlialmers Manufacturing Company, Milwaniree,

Filed Oct. 23, 1962, Ser. No. 232,459 7 Claims. (Cl. 307-885) This invention `relates generally to semiconductor circuits. More specifically this invention relates to a circuit for sequentially gating controlled rectifiers in an inverter.

An inverter provides alternating current from a direct curren-t source. Considered from la rather elementary standpoint, `an inverter 4connects the alternating current load terminals to the direct current source terminals for a half period in one polari-ty and it then reverses the connection for the next half period to provide an alternating volta-ge across the load. Several well Aknown inverter circuits make these connections by means of two semiconductor switch devices for each line of the `alternating current system. One switch device in each pair connects its load terminal to one polarity of the source `and the other switch device connects this load terminal to the other source terminal. A three phase inverter can have six controlled reotiliers that are turned on in a sequence `that maintains each controlled rectifier conducting for one-third lof each cycle. One of the .problems of 4an inverter is to provide means for turning on the `appropriate controlled rectifiers at the preselected point in the alternating current cycle.

One common use for an inverter is to supply a variable frequency to drive a frequency responsive device such as a-n induction motor. Such inverters usually have a variable frequency oscillator that provides .a reference lfor turning on the controlled rectifiers. The requirement to gate the controlled rectifier in response to a frequency reference is la lfurther problem in such .an inverter.

The inverter gating circuit of this invention has a circuit of controlled rectifiers or other devices -that remain conducting once they are turned on. In the gating circuit of 'this invention each controlled rectifier is connected so that whe-n it is turned on, it gates Ian associated switch device in the inverter, turns off the offgoing controlled rectifier of the gating circuit and remains conducting to establish a circ-uit that .controls which controlled rectifier can .be ltur-ned `on next. An oscillator, which may have a variable frequency, provides gating pulses for the controlled rectifiers of the gating circuit.

One advantage of this circuit is that a circuit of diodes establishes the sequence of turning on the controlled rectifiers, and two arrays of diodes can :be provided easily to provide for switching from one phase rotation direction to the other.

One `object of this invention is to provide a new and improved inverter.

Another object of .this invention 4is to provide a new and improved gating circuit for a static inverter.

The dra-wing and the detailed description of the invention will suggest other objects and advantages of the invention.

In the drawing:

IFIG. 1 shows one embodiment of the gating circuit of this invention andan inverter that is connected to be gated by this circuit;

FIG. 2 shows a portion of the gating circuit of FIG. 1; and

FIG. 3 illustra-tes a portion of the circuit of FIG. 1 connected to establish the opposite direction of phase rotation.

The specific circuit that will be described is intended to gate the controlled rectifiers of an inverter 11 ICC (well known). The six controlled rectifiers 10 of inverter 1f1 are suiiixed a through f, and corresponding elements of ythe gating circuit have the same suffixes. Controlled rectifiers -10 are connected to energize 4the cor.- ductors 12 of a three phase system from a direct current source having a positive terminal 13a and va negative terminal 13f. Three of the controlled rectifiers 1061, 10b, 'and 10c can be controlled to connect conductors I12 to the positive terminal 13j and three controlled rectifiers 10d, 10e, and 10jc can be controlled to connect conductors i12 to the negative terminal 13b. One suitable sequence for turning on controlled rectifiers 10 is to initially gate one selected controlled rectifier of each polarity group (e.g., 10a `and I10e), and then 4to gate another controlled rectifier 'of first one polarity group .and then the o-ther. As a controlled rectifier 10 in one group is turned on, it cooperates with other circuit elements to turn loif the previously conducting controlled rectifier |10 of that group.

The gate-cathode circuit of each controlled rectifier 10 is coupled to a stage of ione of two three bit rings 14 and `15 lby mea-ns of a transformer 16. Each stage of rings 14 and I15 has a controlled rectifier 17 that can he turned on (as will he explained later) to connect the primary winding of transformer 16 across the terminals 18 and 19 which are understood to he connected to a direct current source. A capacitor 24 connects the anode terminal `of one controlled rectifier 17 to the anode terminal :of :the next controlled rectifier 17 in the turn on sequence of each ring 14, 15 ffor commutation. A diode 25 is connected across one off the windings lof transformer 16 in the proper polarity to suppress the negative voltage at Ithe .gate terminal 4of fa controlled rectier 10 whe-n controlled rectifier 17 turns off. A resistor 21 is -connected between the gate terminal and the cathode terminal of cont-rolled rectifier 17 to help turn oli controlled rectifier I17. Each stage also includes .an anode resistor 22 and la capacitor 23 that `are connected to shape the voltage wave form across the windings of transformer 16.

The starter circuit A suitable network 30 is provided to turn on a selected stage of each ring when .the circuit is connected lto the source. Network 30 comprises a capacitor 3d and a resistor 62 connected in series across terminals 18, 19 so that an exponentially decaying voltage spike appears across resistor 32 when the circuit is first energized; and a diode 33 -connects the common terminal 34 of capacitor 31 and resistor 32 to the gate terminal of the selected controlled rectifiers 17a and 17e. Diode 33 isolates the gate terminals from capacitor 31 and resistor 32 after the starting pulse. When the gating circuit is deenergized, capacitor 31 discharges in a circuit that may comprise a resistor (not shown) connected across terminals 18, 19. Preferably, each ring 14 and 15 Ihas an independent starting circuit 30.

The oscillator A suitable square wave oscillator 40 provides two gating pulses between a common connection to the negative terminal \19 of the rings .14, -15 and first and second output terminals 41, 42. The oscillator provides a positive polarity gating pulse lat .first one output and then the other. The oscillator preferably comprises a bistable liip rflop that is triggerd by means 0f a relaxation oscillator having a unijunction transistor (well known). A capacitor 43 and a resistor 44 are connected to points 41, 42 to provide voltage spikes of the desi-red width in response to `the positive going edge of the square wave.

The pulse steering circuit The gating pulse at either output 41, 42 of the oscillator is steered to the selected stage `of the two rings llll, 15 by a maze of resistors l50, diodes 51, 52, 53, and Zener diodes 54. The two controlled'rectifiers that are turned on bias the diodes to block the pulses from all but one selected stage of the two rings. FIG..2 shows `a con-- -trolled rectifier t17a, the connections to the oscillator and to they other controlled rectifiers for gating or not gating gate terminal. yEach stage biases one diode 51that pre-v vents the neXt pulse Vifr-om reaching this stage. In FIG. Y2 diode 51 -isshown |in its gate connection and is also shown by dot-dashed lines in its anode connection. Each stage biases one diode '52 that is connected to preventturning on the preceding controlled rectifier 17 in the sequence ofv the same polarity group. Each stage also biases one diode 53 that is connected to prevent turning on one cont-rolled rectifier in the other polarity group to establish which polarity group can receive the next pulse from oscillator 40 A resistor 50 and a Zener diode 54 connect the gate terminal to oscillator output terminal 41. Zener diode`54 is polarized to conduct in its reverse direction only Aif the positive pulse at its cathode terminal is above the breakdown voltage. The diodes 51a, 52a, 53a are connected to maintain the cathode terminal of Zener diode 54a below the breakdown voltage when any selected controlled rectifier (i17a, ^17b, 17d) is turned on. A resistor 50a isolates the potential at the common connection 56a of dio-des 51a, 52a, 53a and Zener diode 54a from the potential at oscillator terminal 41'.

When controlled rect-ifier 17a is turned off, the cathode connection 58a of diodes 51a, 52C, 53d is at the positive potential of the source. The gating pulse at terminals 41, 42 is made less positive than positive terminal 118, Aso* that diodes 51a, 52C, 53d are turned off when controlled rectifier 17a is turned off. Similarly, when diodes 51a, 52a, and 53a are all turned off (i.e., controlled rectifiers 17a, 17b and :17d are all off) a positive pulse at terminal 41 turns on Zener diode 54a and `gates controlled rectifier 17a. Y When controlled rectifier I17a is gated, terminal 58a and the cathodes of diodes 51a, 52C, 53d have substantially the potenti-al of negative terminal 19. Diodes 51a, 52C would turn on 4in response to a positive gating pulse-at terminal 41 and diodes 54, 53d would turn on in response to a positive gating pulse at terminal 42.Y

The diode array shown in FIGS. l and 2 establishes the following sequence for turn-ing on the controlled rectiers: A and E, A and F, B and F, Band D, C and `D, C and E; FIG. 3 shows an array of diodes generally similar to FIG. 2 except that the diodes are connected to establish the reverse phase rotation. Preferably, the gating circuit has an array of diodes lfor each direction of phase rotation. In FIG. 3 the elements not shown in FIG. l are indicated by a prime on the videntifying character. The diode -array illustrated in FIG. 3 can be connected permanently to controlled rectifiers 17 as FIG. 3 shows, and the oscillator output 411,;42 c-an be switched between the two circuits that are illustrated by FIGS. 2 and 3.

Operation Before the circuit is connected to be energized by the source, the capacitors 23, 24, 31 are all discharged. When the circuit is connected to the source, and oscillator 40 is energized, each capacitor 31 charges in series with its resistor 32 -and the positive potential at terminal 34 turns on diodes 33 and gates-controlled rectifiers 17a and 4\1-7e. When controlled rectifiers 17a, `17e turn on, they produce voltage pulses across the transformers 16a, 416e that gate controlled'rectifiers |10a,f10e of the inverter, and they charge capacitors 24a land 24e with terminals SSaVand 58e negative kand terminals 58h and 58f positive. Controlled rectifier 17a puts a low positive potential (negative with respect to a pulse at oscillator terminals 41, 42)

The identifying characters .of diodes 51,152',I

4 f at the cathode terminals of diodes 51a, 52e and 53d to prevent the -first gating pulse from turning ony controlled rectiiiers -17c.or 11'7d land fromregating controlled rectitier 17a. Controlled rectifier -17 similarly blocks the gating circuit to controlled rectifiers` 17h, `1i7d, and 17e. Whenvoscillator 4fiproduces a positive pulse .tfirst at terminal 41 the pulse turns on diodes51tz,;53b and 52C, and the voltageof the pulse. at terminal 41 appears Vacross the resistors 50a, Sfib and 50c and the potential -at the. cathode f terminalszz, 56b, and 56C; of Zener diodes 54a, 54h and 54eV remainsbelow the breakdown voltage and prevents the pulse fromV turningon any of the controlled rectifiers 117e, i17b and 17c; of ring 14. When the positive output pulse of the oscillator appears at terminal 42, Ait'turns the diodes 52d, 53d, ,and 51'e, which prevent'zener diodes 54d and 54e from conducting to gateY controlled rectifiers 17d or 117e'. Thus, the gating potential-at the output'41 appearsat thetcathode terminal of-Zener diode 54j and turns on Zener diode .54)c and gatesl controlled-rectifier, 17j.

When controlled rectifier 171c turns onit` producesy a voltage pulse across the windings of transformer 161, and' it connects the positively charged :terminal 58] of capacitor 24ey to the common negative terminal 19 of ring 15.A Thus, the charge across capacitor 24e appears across the cathode-anode terminals of controlled rectier 17e in the reverse polarity and turns off controlled rectifier 17e'. When controlled rectifier 17e turnsoff, it' removesl the negative potential at the cathode of'diode 531i and thereby establishesa circuit to gate controlled rectifier 17b next.

The capacitors 24 lare made large enough to maintain the reversed potential across the anode-cathode terminals of controlled rectifier 17 long enough that the gating pulse that turned Von'controlled rectifier 17j will not turn on controlled rectifier 17e again.V When controlledzrectifier 17j turns on, it produces'a negative portentiala-t thecathode terminal of the appropriate diodes 51j, 52e and 53o to prevent the next pulse from turning on controlled rectifiers 17C, 17e or from regatingl controlled rectifier 17j.'

Those skilled in :the arti will recognize variations in the. single embodiment of the inventionthatvhas -been described, and the claims are intended to=cover a variety ofy circuits within the spirit of the invention.

Having now particularly described and ascertained the:

nat-ure of my said inventionand the manner in whichit is to be performed, I declare rthat what I claim is:

ionel polarity of a direct current source and a second group of controlled switch devices vassocia-ted with a :second polarity of the source, said gating ,circuit comprising,

a plurality of semiconductor devices each having input terminals and output terminals-,said output terminals |being connected to turn on said controlled switch devices in response to the potential at said output terminals,V

an oscillator for producing, a seriesof pulses to turn on said semiconductor devices, voltage responsive circuit I-means for each fof said semiconductorv means connecting said. oscillator to said f input termin-als, each said circuit means being connectedto selected ones of said output terminals to establish ka conductive 4pathbetween said oscillator andthe input terminals'of only a selected one of said onepolarity of a direct current source and a second group of controlled switch devices associated with a second polarity of the source, said gating circuit comprising,

a first polarity group. and a secondpolarity group of controlled rectifiers, one:V controlled rectifier for each controlled switch device in the inverter, and means-i 1. A gating circuit fory the type 4of inverter lhaving a 1 first group yof controlled switch idevices associated with Y for connecting said controlled rectifiers to turn on the switch devices in -the inverter according to the state of said controlled rectifiers,

an oscillator for producing a series of pulses to turn on said controlled rectifiers,

commutating means interconnecting the controlled rectifiers of each group whereby an on-coming controlled rectier turns off the off-going controlled rectifier in its group,

circuit means for each controlled rectifier connecting its gate terminal to the output of said oscillator, and voltage responsive means in said circuit means for transmitting a gating pulse to its associated controlled rectifier only in response to a predetermined voltage at a point in said circuit means, said circuit means including means isolating the potential of said points from the `corresponding points in the circuit means of the other controlled rectifiers,

means connecting the anode terminals of each of said controlled rectifiers to selected ones of said points to establish selected controlled rec-tifiers that cannot be gated when a given controlled rectifier is turned on, and

means for gating a selected controlled rectifier in each group to start the inverter.

3. A gating circuit for a three phase inverter having a first group of ythree controlled switch devices associated with one polarity of a direct current source and having a second group of three controlled switch devices associated with the other polarity of the source, said gating circuit comprising,

a first polarity group of three controlled rectifiers and a second polarity group of -three controlled rectifiers, each of said controlled rectifiers being connected to cont-rol one of the switch devices in the inverter,

an oscillator providing a series of pulses to tur-n on said controlled rectifiers,

lcommutating means interconnecting said three controlled rectifiers in each group whereby an oncom ing controlled rectifier yturns off any other conducting controlled rectifier in its group,

voltage responsive means connecting the gate terminal of each controlled rectifier to the output of the oscilla-tor only when a terminal of said voltage re sponsive means is at a predetermined voltage, and means for isolating the potential of each said terminal from the terminals of each other of said voltage responsive means,

means connecting a terminal of each controlled rectifier to a terminal of said voltage responsive means of other controlled rectifiers to prevent gating a conducting controlled rectifier, the preceding controlled rectifier in the gating sequence in the same polarity group, or the corresponding controlled rectifier of the opposite polarity group, and

-means for gating two of said controlled rectifiers to start said inverter. 4. A gating circuit for the three phase inverter of the type having a first group of three controlled switch devices -associated with one polarity of a direct current source and having Ia second group of three controlled switch devices associated with the other polarity of the source, said gating circuit comprising,

a first polarity group of three controlled rectifiers and a second polarity group of three controlled rectifiers, each of said controlled rectifiers connected to `control one of the switch devices in said inverter,

an oscillator producing a series of pulses to turn on said controlled rectifiers,

voltage responsive circuit means connecting the gate lterminal of each controlled rectifier to the output of the oscillator for transmitting a pulse to a gate terminal only in response to a predetermined voltage at a point in said circuit means, means in said 6 circuit means isolating the potential of said point from corresponding points in the other of said circuit means, l means including diodes connecting the anode terminal of each controlled rectifier to said point in said circuit means of selected controlled rectifiers to prevent gating a conducting controlled rectifier, the preceding controlled rectifier in the sequence in the same polarity group, or the corresponding controlled rectifier of the opposite polarity group, and commutating means interconnecting said three con- -trolled rectifiers in each group of controlled rectifiers whereby an on-coming controlled rectifier in each group turns ofic any other conducting controlled rectifier in its group. 5. A gating circuit for a three phase inverter having a first group of three controlled switch devices associated with one polarity of a direct current source and having a second group of three controlled switch devices associated with the other polarity of the source, said gating circuit comprising,

a first polarity group of three controlled rectifiers and a second polarity group of three controlled rectifiers, each of said controlled rectifiers being connected to control la switch device in the inverter,

an oscillator producing a pulse alternately at first and second terminals to turn on said controlled rectifiers,

circuit means connecting the gate terminal of each controlled rectifier of said first group to said oscillator first terminal and connecting the gate terminal of each controlled rectifier of said second group to said oscillator second terminal, said circuit means including voltage responsive means `for each said controlled rectifier for transmitting a pulse to a gate Iterminal only in response to a predetermined voltage at .a terminal of said voltage responsive device, means in said circuit means isolating the potential of said terminal from other of said terminals in said circuit means,

means including diodes connecting the anode terminal of each controlled rectifier to selected ones of said terminals in said circuit means to prevent gating either a conducting controlled rectifier or the preceding controlled rectifier in the sequence in the same polarity group, and

commutating means interconnecting said three controlled rectifiers in each group whereby -an on-coming controlled rectifier turns ofi any other conducting controlled lrectifier in its group.

6. A gating circuit for a three phase inverter having a first group of three controlled switch devices associated with one polarity of a direct current source and having la second group of three controlled switch devices associated with the other polarity of the source, said gating circuit comprising,

a first polarity group of three controlled rectifiers 4and a second polarity group of three controlled rectifiers, each of said controlled rectifiers being connected to control a corresponding switch device in the inverter,

an oscillator for producing pulses to turn on said controlled rectifiers,

commutating means interconnecting said three controlled rectifiers in each group of controlled rectifiers whereby any on-coming controlled rectifier turns ofi any other conducting controlled rectifier in its group, said commutating means including a capacitor and a resistor connected to prevent an off-going controlled rectifier from being turned on in the same cycle of the oscillator frequency,

circuit means connecting the gate terminal of each controlled rectifier to rthe output of said oscillator, said circuit means including voltage responsive means for transmitting a pulse t-o the gate terminals only in response to a predetermined voltage at la means including diodes connecting the anode terminal of each controlled rectifier to said point in the; circuit means of selected controlled rectiers to prevent gating a conducting controlled rectifier,; the

preceding controlled rectifier in the sequence .in the same polarity group or the corresponding controlled corresponding points; in theY other ofv said circuit;

means,

means'including diodes connecting; the anode terminal of `'each controlled rectifier to said` point in said circuit means Vof selected controlledrectifiers Vto pre-y vent gating .a conductingcontrolledVL rectifier, the preceding ,controlled rectifier in the sequence inthe samey polarity group, or the, corresponding ycon-f trolled rectifier of the opposite polarity group,

rectifier of the oppositepolarity groupnand 10 means for gating two of said controlled rectifiers to star-t said inverter. 7. A gating circuit for the three phase inverter of the. type having ya first group of three controlled. switch devices associated with one polarity of 'a direct current 15 `sou'rceand having a second group of three controlled switch devices associated with the other polarity of the source, said gating circuit comprising,

a first polarity group of three controlled rectierswand 'a secondpolarity group of three controlled recti- 2()A tiers, each of said controlled rectiers connected to controlqone of the switch devices inthe inverter,

an oscillatorl producing a series of pulses to turn on said controlled rectifiers,

circuit means for each said controlled rectifierV con-V 25 necting its gate terminal to :the output of said oscillator, lsaid circuit means including voltage responsivevrneans for transmitting .a pulse to a gate terminal only in response to a predetermined voltage lat-a point in said circuit means, means in said cir- 30 'cuit means isolatingthe potential of -said pointffrom Icoming icontrolled .rectifier in;eacl1 group turns off any other conducting `controlled rectifier in its `group,

trolled rectifier a capacitor connectingits anode trolled rectifier; in the gatingtsequence in the same rectifier fromy being Yturned ion in :the .sameI cycle and start-said inverter.;

No references cited.A

- ARTHUR GAUSS; Primary Examiner.

I. BUSCH,` 'Assistant i Examiner.

commutating y means interconnecting .said three- Acon; trolled rectiersvin Eeach kgroup, whereby an on` said 'commutatingkmeans including for each con-1 terminal to the anode terminalof ythe next con-A polarity group and including a capacitor; anda re-` sistor connected to shape the voltage wave at said anode: terminal to'prevent thee .off-going controlled.

of said oscillator in which `it has; been turned voth:

means for gating two of said controlled frectiers to 

1. A GATING CIRCUIT FOR THE TYPE OF INVERTER HAVING A FIRST GROUP OF CONTROLLED SWITCH DEVICES ASSOCIATED WITH ONE POLARITY OF A DIRECT CURRENT SOURCE AND A SECOND GROUP OF CONTROLLED SWITCH DEVICES ASSOCIATED WITH A SECOND POLARITY OF THE SOURCE, SAID GATING CIRCUIT COMPRISING, A PLURALITY OF SEMICONDUCTOR DEVICES EACH HAVING INPUT TERMINALS AND OUTPUT TERMINALS, SAID OUTPUT TERMINALS BEING CONNECTED TO TURN ON SAID CONTROLLED SWITCH DEVICES, IN RESPONSE TO THE POTENTIAL AT SAID OUTPUT TERMINALS, AN OSCILLATOR FOR PRODUCING A SERIES OF PULSES TO TURN ON SAID SEMICONDUCTOR DEVICES, VOLTAGE RESPONSIVE CIRCUIT MEANS FOR EACH OF SAID SEMICONDUCTOR MEANS CONNECTING SAID OSCILLATOR TO SAID INPUT TERMINALS, EACH SAID CIRCUIT MEANS BEING CONNECTED TO SELECTED ONES OF SAID OUTPUT TERMINALS TO ESTABLISH A CONDUCTIVE PATH BETWEEN SAID OSCILLATOR AND THE INPUT TERMINALS OF ONLY A SELECTED ONE OF SAID SEMICONDUCTOR DEVICES ACCORDING TO THE CONDUCTION STATE OF ALL OF SAID SEMICONDUCTOR DEVICES, AND MEANS INTERCONNECTING SAID OUTPUT TERMINALS WHEREBY AN ON-COMING SEMICONDUCTOR DEVICE TURNS OFF THE OFFGOING SEMICONDUCTOR DEVICE IN A PRESET SEQUENCE. 